Applications with large memory footprints, like SAP HANA, can often stress the hardware memory subsystem (that is, Translation Lookaside Buffer, or TLB) with their access patterns. Modern processors can mitigate this performance impact by creating larger mappings to memory and increasing the memory reach of the application. In prior releases, ESXi allowed guest operating system memory mappings based on 2 MB page sizes. This release introduces memory mappings for 1 GB page sizes.

As shown in the following figure, there is up to 26% improvement in 1 GB memory access performance, compared to 2 MB page size, through more efficient use of the TLB and processor L1-L3 cache.

The host with an access size of 1 GB performed 26% better than the host with an access size of 2 MB

 

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